The present invention generally relates to digital electronic dual port random access memory cells, and more specifically relates to a 6-transistor complementary metal oxide semiconductor implementation thereof such dual port random access memory cells.
Dual port random access to a memory means that a random access memory has two independent data and address paths for access to each memory cell. Ths duality allows the accessing of the memory cell by two different paths simultaneously. Since each access port is independent of the other, both ports can be operated at the same or (asynchronously) at different data rates. One utility of such a dual port random access memory (dual port RAM) is that it enables data to be passed between asynchronous microprocessors without establishing a handshake model such as slows down the faster processor. With the dual port RAM device the faster processor can store, through a first "A" port, data into the dual port RAM, where such data can later be accessed through a second "B" port by a slower processor operating at a slower rate. Dual port RAM's are also useful as a first-in, first-out (FIFO) memories wherein the dual port RAM is a storage element often implemented in using gate array logic.
A prior art example of the implementation of a dual port RAM in transistor-transistor logic is represented by the Advanced Micro Devices AM 2903 microprocessor device, available from Advanced Micro Devices. Another prior art implementation, a dual port end-channel MOS random-access-memory chip of Bell Laboratories, Allentown, Pa. is described in the Oct. 6, 1982 issued of ELECTRONICS Magazine at page 47. Both these prior art references generally discuss the logical characteristics, and the manner of addressing and reading and writing, a dual port RAM.
A prior art implementation of a complementary metal oxide semiconductor technology, dual port random access memory, such as is the subject of applicants' invention, is taught in the paper CMOS DUAL PORT RAM MASTERSLICE by Stephen Glen Bowers of the Storage Technology Corporation appearing in the proceedings of the 1982 CUSTOM INTEGRATED CIRCUITS CONFERENCE of the IEEE at pages 311-314. The implementation presented is a combination of a CMOS 128.times.9 dual port static ram, 586 2-input gate equivalent blocks of CMOS logic gate array, 96 I/O pads and 8 power pads implemented as a master slice in 3 micron poly gate, oxide isolated complementary metal oxide semiconductor process. Of particular interest to the present invention, the memory cell which is the building block of the dual port RAM is comprised of 8 transistors. Additionally, the 8 transistor dual port implementation of the RAM cell will demonstrate unequal capacitance, and resultantly unequal signals, to each of the two, A and B, port bit lines dependent upon whether a single one, or both, of such two ports are being read at the same time. This dual, and/or asynchronous A and B port readings is not prohibited in the prior art embodiment, however, the bit line signals sensed at the outputs of the cell will be variant dependent upon whether such cell is being read at one only, or at both, ports. Finally, the prior art cell will prove to exhibit much more parasitic capacitance on the bit lines connected thereto than the dual port RAM cell of the present invention.